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STHV748
5-level, 90 V, 2 A high-speed pulser with four independent channels
Preliminary data
Features

High-density ultrasound transmitter 0 to 90 V output voltage Up to 20 MHz operating frequency Low-power, high-voltage drivers 2 independently supplied half bridges for each channel in pulse wave (PW) mode - 5-level output waveform - 2 A source and sink current - Down to 20 ps jitter - Anti-cross conduction function - Low 2nd harmonic distortion - Fine-tuning on propagation delay Fully integrated clamping-to-ground function - 6 synchronous active clamp - Anti-leakage on output node Dedicated half bridge for continuous wave (CW) mode on each - Down to 0.1 W power consumption - 0.6 A source and sink current - Down to 10 ps jitter Fully integrated HV receiver switch - 13.5 on resistance - HV MOS topology to minimize current consumption - Up to 300 MHz BW 2.4 V to 3.6 V CMOS logic interface Auxiliary integrated circuits - Noise blocking diodes - Fully self-biaising architecture - Anti-memory effect for all internal HV nodes - Thermal protection - Stand by function Latch-up free due to HV SOI technology Very few external passive components needed QFN64 9 x 9 x1.0 mm
Applications

Medical ultrasound imaging Pulse waveform generator NDT ultrasound transmission Piezoelectric transducers driver
Description
This monolithic, high-voltage, high-speed pulser generator features four independent channels. It is designed for medical ultrasound applications, but can also be used for other piezoelectric, capacitive or MEMS transducers. The device comprises a controller logic interface circuit, level translators, MOSFET gate drivers, noise blocking diodes and high-power P-channel and N-channel MOSFETs as output stage for each channel, clamping-to-ground circuitry, anti-leakage, antimemory effect block, thermal sensor and HV receiver switch (HVR_SW) which guarantees a strong decoupling during transmission phase. Moreover the STHV748 includes self biasing and thermal shutdown blocks (see Figure 1). Each channel can support up to five active output levels with two half bridges. The output stage of each channel is able to provide 2 A peak output current. In order to reduce power dissipation during continuous wave mode, the peak current is limited to 0.6 A (a dedicated half bridge is used). Table 1. Device summary
Package QFN64 Packaging Tape and reel 1/22
www.st.com 22

Order code STHV748QTR
January 2010
Doc ID 15450 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STHV748
Contents
1 2 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Additional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 4 5
Truth table and single channel block description . . . . . . . . . . . . . . . . . 7 Typical supply reference setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Operating supply voltages and average currents . . . . . . . . . . . . . . . . 10
6.1 6.2 Digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 8 9 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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STHV748
Typical application circuit
1
Typical application circuit
Figure 1. Typical application circuit
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Pin settings
STHV748
2
2.1
Pin settings
Connection
Figure 2. Pin connection (top view)
Note:
0.25 mm X 100 V maximum voltage between abutted pins
2.2
Description
Table 2.
Pin N 1 2 3 4 5 6 7 8 9 10 11
Pin description (P = power, A = analog, D = digital)
Name AGND REF_HVM1 HVM1_A HVM0_A HVOUT_A HVP0_A REF_HVP1 HVP1_A HVP1_B REF_HVP0 HVP0_B Signal ground Supply for low side 1 gate driver Negative high-voltage supply 1 channel A Negative high-voltage supply 0 channel A Channel A, high-voltage output before noise blocking diodes Positive high-voltage supply 0 channel A Supply for high side 1 gate driver Positive high-voltage supply 1 channel A Positive high-voltage supply 1 channel B Supply for high side 0 gate driver Positive high-voltage supply 0 channel B Function IN/OUT I I I I O I I I I I I Type A P P P P P P P P P P
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STHV748 Table 2.
Pin N 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin settings Pin description (P = power, A = analog, D = digital) (continued)
Name HVOUT_B HVM0_B HVM1_B REF_HVM0 D_CTR IN4 IN1_B IN2_B IN3_B VDDP GND_PWR XDCR_B LVOUT_B LVOUT_C XDCR_C GND_PWR VDDM IN3_C IN2_C IN1_C THSD AGND REF_HVM1 HVM1_C HVM0_C HVOUT_C HVP0_C REF_HVP1 HVP1_C HVP1_D REF_HVP0 HVP0_D HVOUT_D Function Channel B, high-voltage output before noise blocking diodes Negative high-voltage supply 0 channel B Negative high-voltage supply 1 channel B Supply for low side 0 gate driver Delay control Input signal shared Input signal channel B Input signal channel B Input signal channel B Positive low-voltage supply Power ground Channel B, high-voltage output Channel B, low-voltage output Channel C, low-voltage output Channel C, high-voltage output Power ground Negative low-voltage supply Input signal channel C Input signal channel C Input signal channel C Thermal shutdown pin Signal ground Supply for low side 1 gate driver Negative high-voltage supply 1 channel C Negative high-voltage supply 0 channel C Channel C, high-voltage output before noise blocking diodes Positive high-voltage supply 0 channel C Supply for high side 1 gate driver Positive high-voltage supply 1 channel C Positive high-voltage supply 1 channel D Supply for high side 0 gate driver Positive high-voltage supply 0 channel D Channel D, high-voltage output before noise blocking diodes IN/OUT O I I I I I I I I I I O O O O I I I I I I/O I I I I O I I I I I I O Type P P P P A D D D D A P P A A P P A D D D D A P P P P P P P P P P P
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Pin settings Table 2.
Pin N 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
STHV748 Pin description (P = power, A = analog, D = digital) (continued)
Name HVM0_D HVM1_D REF_HVM0 DGND DVDD IN1_D IN2_D IN3_D VDDP GND_PWR XDCR_D LVOUT_D LVOUT_A XDCR_A GND_PWR VDDM IN3_A IN2_A IN1_A EN Function Negative high-voltage supply 0 channel D Negative high-voltage supply 1 channel D Supply for low side 0 gate driver Logic ground Positive logic supply Input signal channel D Input signal channel D Input signal channel D Positive low-voltage supply Power ground Channel D, high-voltage output Channel D, low-voltage output Channel A, low-voltage output Channel A, high-voltage output Power ground Negative low-voltage supply Input signal channel A Input signal channel A Input signal channel A Enable internal supply generators Substrate IN/OUT I I I I I I I I I I O O O O I I I I I I I Type P P P A A D D D A P P A A P P A D D D D P
Exposed-Pad
2.3
Additional pin description
EN allows minimizing the power consumption. If EN=0, the self voltage reference is not supplied. Supplying reference externally the total power consumption is reduced. THSD is a thermal flag. The output stage of THSD pin is a Nch-MOS open-drain, so this necessary to connect external pull-up resistance (Rp10 k) to positive low-voltage supply (see Figure 1).If the internal temperature overtakes 160 C, THSD goes down and put all the channels in HZ state. Externally forcing THSD to positive low-voltage supply, the thermal protection will be disabled. D_CTR can be used to optimize 2nd HD performances by tuning the fall propagation delay (tdf - see table 9). If D_CTR is equal to ground tdf has the nominal value. If D_CTR is being varied from 2 V to 4.2 V tdf can be changed from -1ns to +600 ps respect to the nominal value. EXPOSED-PAD is internally connected to the substrate. It can be floating or connected to a 100 V capacitance toward ground in order to reduce noise during the receiving phase.
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STHV748
Truth table and single channel block description
3
Truth table and single channel block description
Figure 3. Single channel block description
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Typical supply reference setting
STHV748
Table 3.
Global
Truth table for one channel
Per channel State
Switches internal state
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 Clamp HVM0 HVP0 HVR_SW HVP1 HZ HVR_SW Max HVM0 and HVM1 Max HVP0 and HVP1 CW HVM1 CW HVP1 HZ 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0
THSD IN4 IN3 IN2 IN1 1 1 1 1 1 1 1 1 1 1 1 0 x 0 0 x 0 0 1 1 1 1 1 x x 0 0 0 1 1 1 0 0 1 1 x 0 0 1 1 1 1 1 0 1 0 1 x 0 1 0 1 0 1 1 1 0 1 0 x
4
Typical supply reference setting
Table 4.
Symbol EN Cp0, Cp1 Cn0, Cn1 REF_HVP# REF_HVM#
Typical supply reference setting
External supply mode 0 Not used Not used Has to be connected to HVP# -3 V Has to be connected to HVM# +3 V Self supply mode 1 47 nF(1) 9 nF (1) Not used Not used
1. In Self supply mode 30 s after EN edge to charge external capacitance are needed.
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STHV748
Electrical data
5
5.1
Electrical data
Absolute maximum ratings
Table 5.
Symbol AGND DGND GND_PWR VDDP VDDM DVDD HVP0 HVP1 HVM0 HVM1
Absolute maximum ratings
Parameter Analog ground reference (1) Digital ground Power ground Positive supply voltage Negative supply voltage Positive logic voltage TX0 high-voltage positive supply TX1 high-voltage positive supply TX0 high-voltage negative supply TX1 high-voltage negative supply Value 0 -300 to 300 -1.2 to 1.2 -0.3 to 3.9 0.3 to -3.9 -0.3 to 3.9 0 to 95 HVP0 0 to -95 HVM0 -0.3 < HVP - REF_HVP < 3.3 -0.3 < REF_HVM - HVM < 3.3 -95 to 95 -95 to 95 -1 to 1 -0.3 to DVDD + 0.3 -0.3 to 4.6 -40 to 125 -65 to 150 Unit V mV V V V V V V V V V V V V V V V C C
REF_HVP# High-voltage positive gate supply REF_HVM# High-voltage negative gate supply XDCR HVOUT LVOUT DIG I/O D_CTR TOP TSTG High-voltage output High-voltage output before noise blocking diodes Low-voltage output Digital input specified in tab1 Delay control Operating temperature range Storage temperature range
1. AGND is considered like "ground reference" for all fallen voltages.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 6.
Symbol Rth,JA Parameter Thermal resistance junction-amb Value 30 (1) Unit C/W
1. This value is given for a two layer PCB (252P) and it's strongly sensitive to PCB layout. Increasing the number of PCB layer or adding heat singer vias this number degree (reduce)
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Operating supply voltages and average currents
STHV748
6
Table 7.
Symbol VDDP IVDDP IVDDP_Q VDDM IVDDM IVDDM_Q DVDD I_DVD I_DVD_Q HVP IHVP IHVP_Q HVM IHVM IHVM_Q
Operating supply voltages and average currents (a)
Supply voltages
Parameter Positive supply voltage PW mode Positive supply current Stand-by mode Negative supply voltage PW mode Negative supply current Stand-by mode Positive logic voltage PW mode Logic supply current Stand-by mode High-voltage positive supply PW mode HV positive supply current Stand-by mode High-voltage negative supply PW mode HV negative supply current Stand-by mode 2.7 PW mode HV positive REF current Stand-by mode 200 2.7 PW mode HV negative REF current Stand-by mode Ground reference PW mode Analog ground current Stand-by mode Power ground reference PC mode PWR ground current Stand-by mode Delay control 0 1 4.2 A V
(3) (1) (2)
Conditions
Min 2.7
Typ 3
Max 3.6 3 1
Units V mA A V mA A V A A V mA A V mA A V mA A V mA A V
-2.7
-3
-3.6 2 1
2.4
3
min(3.6,VDDP+0.3) 10
55 0
65
80 90 50 1
-90
0 45 1 3 3.3 7 300 3 400 3.3 3
HVP-REF_HVP High-voltage positive gate supply IREF_HVP IREF_HVP_Q REF_HVM-HVM High-voltage negative gate supply IREF_HVM IREF_HVM_Q AGND IAGND IAGND_Q GND_PWR IGND_PWR IGND_PWR_Q D_CTR
200
300 0
400
700 1 0 20
A A V mA
1. In PW pulse wave mode the average current is measured over 5 periods (see Figure 5) 2. In Stand-by mode all channels are in HZ. 3. In PC pulse cancellation mode the average current is measured over 1 period (see Figure 6)
a. Operation conditions, unless otherwise specified, only A channel on, no load, HV=90V, TX0 and TX1 on, EN=0.
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STHV748
Operating supply voltages and average currents
6.1
Digital inputs
Table 8. Digital inputs
Symbol IN1_#, IN2_#, IN3_#, IN4, EN, THSD IN1_#, IN2_#, IN3_#, IN4, EN, THSD Parameter Input logic high-voltage Input logic low-voltage Min. 0.8DVDD 0 Max. DVDD 0.2DVDD Units V V
6.2
Output signals
Table 9.
Symbol
Output signals
Parameter Min. -90 -90 -1 0 Max. 90 90 1 3 Units V V V V
HVOUT High-voltage output before noise blocking diodes XDCR High-voltage output
LVOUT Low-voltage output THSD Thermal shutdown pin
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Electrical characteristics
STHV748
7
Table 10.
Symbol
Electrical characteristics
Static electrical characteristics (1)
Parameter Condition HVP# =10V, HVM# =-10V, HVOUT=0V IN Saturation current S1 - S3 HVP# =25V, HVM# =-25V, HVOUT=0V HVP# =10V, HVM# =-10V, HVOUT=0V IP Saturation current S0 - S2 HVP# =25V, HVM# =-25V, HVOUT=0V Saturation current S5 Saturation current S4 HVP1=10V, HVM1=-10V, HVOUT=0V HVP1=10V, HVM1=-10V, HVOUT=0V 315 415 1.25 1.70 350 480 1.54 TBD 1.32 1.59 TBD 1 4 126 25 0.8VDDP 0.8VDDP 130 145 40 40 11.5 1 13.5 15.5 30 4.5 150 40 1.2VDDP 1.2VDDP 160 A W mW mW V V C C pF G 2 400 575 2 A mA mA A A 1.12 1.70 1.26 1.42 A A Min 1.18 Typ 1.28 Max 1.40 Units A
INCW IPCW
Positive saturation current HVOUT=10V S6 (Pch) HVOUT=25V ICL Negative saturation current S6 (Nch) IL Output leakage current, per channel HVOUT=10V HVOUT=25V HVP# = 90V, HVM# = -90V, HVOUT=0V
PSB
HVP# = 90V, HVM# = -90V, Power dissipation in stand HVOUT=0V, EN=0 by mode HVP# = 90V, HVM# = -90V, HVOUT=0V Power dissipation in HVR_SW state HVP# - REF_HVP# REF_HVM# - HVM# Over temperature threshold OTP Hysteresis HVR_SW capacitance HVP# = 90V, HVM# = -90V, EN=0, all channels in receiving phase HVP# = 90V, HVM# = -90V, HVOUT=0V HVP# = 90V, HVM# = -90V, HVOUT=0V HVP# =10V, HVM# =-10V HVP# =10V, HVM# =-10V LVOUT=0V HVP# =10V, HVM# =-10V, XDCR=1V, LVOUT=0V HVP# =10V, HVM# =-10V, XDCR=1V, LVOUT=0V
PRX VREFP VREFN TOTP THYS CHVR_SW
RHVR_SW_ON RHVR_SW on resistance RHVR_SW_OFF RHVR_SW off resistance
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STHV748 Table 10.
Symbol
Electrical characteristics Static electrical characteristics (1) (continued)
Parameter Voltage drop between HVP1 and XDCR Condition HVP# =10V, HVM# =-10V, ISINK_XDCR=50mA HVP# =10V, HVM# =-10V, ISOURCE_XDCR=50mA Min 2.62 2.69 Typ 2.79 2.86 Max 2.96 3.03 Units V V
VDROP_CW
Voltage drop between XDCR and HVM1
1. Operating conditions, unless otherwise specified, EN = 1, HVP# = 90 V, HVM# = -90 V, VDDP = 3 V, VDDM = - 3 V, DVDD = 3 V, TROOM = 25 C.
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Electrical characteristics
STHV748
Table 11.
Symbol f
AC electrical characteristics (1)
Parameter Maximum output frequency 50pF//200 22 20 MHz MHz HVP1 =5V, HVM1 = -5V, continuous wave mode HVP1 = 50V, HVM1 = -50V, continuous wave mode, 50pF//200 Test condition Min Typ Max 16 Units MHz
fCW
Maximum output frequency CW
fBW tj tj-CW tf tr tdr tdf tHVR_SW
Output frequency BW Output jitter CW output jitter Fall time Rise time Rise propagation delay Fall propagation delay HVR_SW turn-on / turn-off time
10 20
MHz ps, rms ps, rms 31 31 27 27 ns ns ns ns ns dBc -40 dBc dBc -40 dBc dBc -40 dBc % 70 mW mVpp db
HVP1 =10V, HVM1 = -10V, continuous wave mode
5 28 28 24 24 170
1 pulse f = 1.7MHz HD2 2nd harmonic distortion 1 pulse f = 5MHz 5 pulses f = 1.7MHz 5 pulses f = 5MHz f = 1.7MHz original and inverted pulse HD2PC Pulse cancellation f = 5MHz original and inverted pulse BVD PD_CW Burst voltage drop Power dissipation, per channel 1st to 128th pulse HVP1 = 10V, HVM1 = -10V CW mode, f = 5MHz, HVP1 = 5V, HVM1 = -5V, no load -60 -60 -60
-40
-40
-40
2
HVR_SWSPIKE HVR_SW spike on XDCR and LVOUT XTALK Cross talk between channels. Ampl(2ch)/Ampl(1ch), 50pF//200
100 -40
1. Operating conditions, unless otherwise specified, HVP# = 90V, HVM# = -90V, VDDP = 3V, VDDM = -3V, DVDD = 3V, EN = 0, (HVP-REF_HVP) = 3V, (REF_HVM-HVM) = 3V, XDCR load C = 300pF//R = 100, LVOUT load C = 20pF//200 TROOM = 25 C.
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STHV748
Timings
8
Timings
Figure 4. tr, tf, tdr and tdf descriptions
Figure 5.
PW example 5 periods, HVP0 = 90 V HVM0 = -90 V, T=200 ns, T_tx=1.2 s
Figure 6.
PW and HD2 example (HVP0=80V, HVM0=-80 V load 300 pF//100 )
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Timings Figure 7.
STHV748 PC example, HVP0 = 90 V HVM0 = -90 V, T=200 ns, T_pos= T_neg=400 ns
Figure 8.
PC and HD2 example (HVP0=60 V, HVM0=-60 V load 300 pF//100 )
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STHV748 Figure 9.
Timings CW mode example, HVP1 = 5 V, HVM1 = 5 V, T = 200 ns, T_tx>1 ms
Figure 10. HVR_SW bandwidth
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Package mechanical data
STHV748
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Table 12.
Dim A A1 A2 A3 b D D1 D2 E E1 E2 e L P K ddd 0.35 8.85 0.18 8.85
QFN64 9 x 9 x 1.0 mm 64 pitch 0.50 mechanical data
Min. 0.8 Typ. 0.9 0.02 0.65 0.2 0.25 9 8.75 See exposed pad variation 9 8.75 See exposed pad variation 0.5 0.4 0.45 0.6 12 0.08 9.15 0.3 9.15 Max. 1 0.05 1
Table 13.
Exposed-pad variation
D2 E2 Max. 4.4 4.85 7.25 7.45 Min. 4.1 4.55 6.95 7.15 Typ. 4.25 4.7 7.1 7.3 Max. 4.4 4.85 7.25 7.45
Variation Min. A B C D 4.1 4.55 6.95 7.15 Typ. 4.25 4.7 7.1 7.3
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STHV748 Figure 11. QFN64 9 x 9 x 1.0 mm 64 pitch 0.50 drawing
Package mechanical data
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Package mechanical data Figure 12. QFN64 9 x 9 x 1.0 mm 64 tape and reel information
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 12.25 12.25 2.1 3.9 15.9 12.8 20.2 60 30.4 12.45 12.45 2.3 4.1 16.1 0482 0482 0.083 0.153 0.626 TYP MAX. 330 13.2 0.504 0.795 2.362 MIN. TYP. inch
STHV748
MAX. 12.992 0.519
1.196 0.490 0.490 0.091 0.161 0.639
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STHV748
Revision history
10
Revision history
Table 14.
Date 20-Jan-2010
Document revision history
Revision 1 Initial release Changes
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STHV748
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